ridm@nrct.go.th   ระบบคลังข้อมูลงานวิจัยไทย   รายการโปรดที่คุณเลือกไว้

Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}
นักวิจัย : Tay, Thian Fatt , Chang, Chip-Hong , Low, Jeremy Yung Shern
คำค้น : DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2556
อ้างอิง : Tay, T. F., Chang, C.-H., & Low, J. Y. S. (2013). Efficient VLSI Implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}. IEEE transactions on very large scale integration (VLSI) systems, 21(10), 1936-1940. , 1063-8210 , http://hdl.handle.net/10220/25187 , http://dx.doi.org/10.1109/TVLSI.2012.2221752 , 168511
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on very large scale integration (VLSI) systems
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

Scaling is a problematic operation in residue number system (RNS) but a necessary evil in implementing many digital signal processing algorithms for which RNS is particularly good. Existing signed integer RNS scalers entail a dedicated sign detection circuit, which is as complex as the magnitude scaling operation preceding it. In order to correct the incorrectly scaled negative integer in residue form, substantial hardware overheads have been incurred to detect the range of the residues upon magnitude scaling. In this brief, a fast and area efficient 2n signed integer RNS scaler for the moduli set {2n-1, 2n, 2n+1} is proposed. A complex sign detection circuit has been obviated and replaced by simple logic manipulation of some bit-level information of intermediate magnitude scaling results. Compared with the latest signed integer RNS scalers of comparable dynamic ranges, the proposed architecture achieves at least 21.6% of area saving, 28.8% of speedup, and 32.5% of total power reduction for n ranging from 5 to 8.

บรรณานุกรม :
Tay, Thian Fatt , Chang, Chip-Hong , Low, Jeremy Yung Shern . (2556). Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Tay, Thian Fatt , Chang, Chip-Hong , Low, Jeremy Yung Shern . 2556. "Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Tay, Thian Fatt , Chang, Chip-Hong , Low, Jeremy Yung Shern . "Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2556. Print.
Tay, Thian Fatt , Chang, Chip-Hong , Low, Jeremy Yung Shern . Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2556.