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0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance
นักวิจัย : Do, Anh Tuan , Yin, Chun , Velayudhan, Kavitha , Lee, Zhao Chuan , Yeo, Kiat Seng , Kim, Tony Tae-Hyoung
คำค้น : DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2557
อ้างอิง : Do, A. T., Yin, C., Velayudhan, K., Lee, Z. C., Yeo, K. S., & Kim, T. T. H. (2014). 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance. IEEE journal of solid-state circuits, 49(7), 1487-1498. , http://hdl.handle.net/10220/20473 , http://dx.doi.org/10.1109/JSSC.2014.2316241
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE journal of solid-state circuits
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the delay of the sense amplifier enable signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum ML swing, making the CAM tolerant to variations. The proposed ABC scheme achieves the power reduction of 5.5× compared with the conventional ML sensing scheme. In addition, multi-V t transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharging speed by 2× when compared with the standard-V t devices at 1.2 V, 80 °C. A test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 1.2 V/500 MHz.

บรรณานุกรม :
Do, Anh Tuan , Yin, Chun , Velayudhan, Kavitha , Lee, Zhao Chuan , Yeo, Kiat Seng , Kim, Tony Tae-Hyoung . (2557). 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Do, Anh Tuan , Yin, Chun , Velayudhan, Kavitha , Lee, Zhao Chuan , Yeo, Kiat Seng , Kim, Tony Tae-Hyoung . 2557. "0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Do, Anh Tuan , Yin, Chun , Velayudhan, Kavitha , Lee, Zhao Chuan , Yeo, Kiat Seng , Kim, Tony Tae-Hyoung . "0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2557. Print.
Do, Anh Tuan , Yin, Chun , Velayudhan, Kavitha , Lee, Zhao Chuan , Yeo, Kiat Seng , Kim, Tony Tae-Hyoung . 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2557.