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Design of ultra-low-power 60-GHz direct-conversion receivers in 65-nm CMOS

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : Design of ultra-low-power 60-GHz direct-conversion receivers in 65-nm CMOS
นักวิจัย : Cai, Deyun , Shang, Yang , Yu, Hao , Ren, Junyan
คำค้น : DRNTU::Engineering::Electrical and electronic engineering.
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2556
อ้างอิง : Cai, D., Shang, Y., Yu, H., & Ren, J. (2013). Design of ultra-low-power 60-GHz direct-conversion receivers in 65-nm CMOS. IEEE Transactions on Microwave Theory and Techniques, 61(9), 3360-3372. , 0018-9480 , http://hdl.handle.net/10220/19256 , http://dx.doi.org/10.1109/TMTT.2013.2268738
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on microwave theory and techniques
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

This paper has explored an ultra-low-power design of two 60-GHz direct-conversion receivers in a 65-nm CMOS process for single-channel and multi-channel applications under the IEEE 802.15.3c standard, respectively. One subthreshold biasing 0.4-V transconductance mixer is designed with a compact quadrature hybrid coupler (160 μm × 210 μm with measured 3-dB intrinsic loss) in receivers to achieve low power (8 mW for single channel and 12.4 mW for multi-channel) and high gain (55 dB for single channel and 62-dB for multi-channel). One three-stage low-noise amplifier employs high- Q passive matchings. A double-layer-stacked inductor is utilized for matching in the single-channel receiver and a high-impedance transmission line is utilized for matching in the multi-channel receiver, respectively. In addition, one new modified Cherry-Hooper amplifier is applied for the variable-gain amplifier design to achieve high gain-bandwidth product and high power efficiency. The single-channel receiver is implemented with 0.34- mm2 chip area. It is measured with a power consumption of 8 mW, a minimum single-sideband noise figure (NF) of 4.9 dB, a 3-dB bandwidth of 3.5 GHz, and a maximum conversion gain of 55 dB. The multi-channel receiver is implemented with 0.56- mm2 chip area. It is measured with a power consumption of 12.4 mW, a 3-dB bandwidth of 8 GHz (59.5 ~ 67.5 GHz), and a maximum conversion gain of 62 dB. The measurement results show that the two demonstrated 60-GHz direct-conversion receivers can achieve high gain and low NF with ultra-low power in 65-nm CMOS.

บรรณานุกรม :
Cai, Deyun , Shang, Yang , Yu, Hao , Ren, Junyan . (2556). Design of ultra-low-power 60-GHz direct-conversion receivers in 65-nm CMOS.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Cai, Deyun , Shang, Yang , Yu, Hao , Ren, Junyan . 2556. "Design of ultra-low-power 60-GHz direct-conversion receivers in 65-nm CMOS".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Cai, Deyun , Shang, Yang , Yu, Hao , Ren, Junyan . "Design of ultra-low-power 60-GHz direct-conversion receivers in 65-nm CMOS."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2556. Print.
Cai, Deyun , Shang, Yang , Yu, Hao , Ren, Junyan . Design of ultra-low-power 60-GHz direct-conversion receivers in 65-nm CMOS. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2556.