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Through silicon via fabrication with low-κ dielectric liner and its implications on parasitic capacitance and leakage current

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : Through silicon via fabrication with low-κ dielectric liner and its implications on parasitic capacitance and leakage current
นักวิจัย : Zhang, Lin , Lim, Dau Fatt , Li, Hong Yu , Gao, Shan , Tan, Chuan Seng
คำค้น : DRNTU::Engineering::Electrical and electronic engineering.
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2555
อ้างอิง : Zhang, L., Lim, D. F., Li, H. Y., Gao, S., & Tan, C. S. (2012). Through Silicon Via Fabrication with Low-κ Dielectric Liner and Its Implications on Parasitic Capacitance and Leakage Current. Japanese Journal of Applied Physics, 51. , 0021-4922 , http://hdl.handle.net/10220/11653 , http://dx.doi.org/10.1143/JJAP.51.04DB03
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : Japanese journal of applied physics
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

Through silicon via (TSV) has emerged as an essential enabler for three-dimensional integrated circuit (3D IC). The basic TSV structure consisting of a via hole in the Si substrate filled with metal such as copper and lined with a dielectric liner, forms a metal–oxide–silicon (MOS) capacitor structure. To benefit the performance of 3D IC, the TSV used to interconnect vertically stacked dies must introduce small electrical parasitic, such as capacitance. The isolation property of the dielectric liner must also be preserved to control the leakage current. In this work, TSV with acceptable sidewall roughness is achieved and lined with low-κ material with an effective dielectric constant of ∼2.8. Low-κ liner with conformal step coverage is successfully achieved in our fabrication process. Based on electrical measurement, it is found that the integration of the low-κ liner reduces the TSV capacitance by ∼27.6% as compared with the conventional plasma-enhanced tetraethylorthosilicate (PETEOS) oxide liner. In addition, current–voltage (I–V) measurement is carried out to monitor and study the leakage of the low-κ liner. No abrupt breakdown is observed until at least at an electric field of 3 MV/cm which corresponds to 60 V. Annealing of the TSV structure in forming gas (N2/H2) at 350 °C for 30 min successfully reduces the leakage current density by ∼1.6×, to a mid-distribution value of ∼6.8×10-6 A/cm2.

บรรณานุกรม :
Zhang, Lin , Lim, Dau Fatt , Li, Hong Yu , Gao, Shan , Tan, Chuan Seng . (2555). Through silicon via fabrication with low-κ dielectric liner and its implications on parasitic capacitance and leakage current.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Zhang, Lin , Lim, Dau Fatt , Li, Hong Yu , Gao, Shan , Tan, Chuan Seng . 2555. "Through silicon via fabrication with low-κ dielectric liner and its implications on parasitic capacitance and leakage current".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Zhang, Lin , Lim, Dau Fatt , Li, Hong Yu , Gao, Shan , Tan, Chuan Seng . "Through silicon via fabrication with low-κ dielectric liner and its implications on parasitic capacitance and leakage current."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2555. Print.
Zhang, Lin , Lim, Dau Fatt , Li, Hong Yu , Gao, Shan , Tan, Chuan Seng . Through silicon via fabrication with low-κ dielectric liner and its implications on parasitic capacitance and leakage current. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2555.