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An area and energy efficient inner-product processor for serial-link bus architecture

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : An area and energy efficient inner-product processor for serial-link bus architecture
นักวิจัย : Meher, Manas Ranjan , Jong, Ching Chuen , Chang, Chip Hong
คำค้น : DRNTU::Engineering::Electrical and electronic engineering
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2555
อ้างอิง : Meher, M. R., Jong, C. C., & Chang, C. H. (2012). An area and energy efficient inner-product processor for serial-link bus architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(12), 2945-2955. , 1549-8328 , http://hdl.handle.net/10220/11317 , http://dx.doi.org/10.1109/TCSI.2012.2220471
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on circuits and systems I : regular papers
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

A unique word-serial inner-product processor architecture is proposed to capitalize on the high-speed serial-link bus. To eliminate the input buffers and deserializers, partial products are generated immediately from the serial input data and accumulated by an array of small binary counters operating in parallel to form a reduced partial product matrix directly. The height of the resultant partial product matrix is reduced logarithmically, and hence the carry-save-adder tree needed to complete the inner-product computation is smaller and faster. The small binary counters act as active on-chip buffers to mitigate the workload of the partial product accumulator. Their ability to accumulate partial product bits faster than combinatorial full adder leads to a simple two-stage architecture of high throughput and low latency. The architecture consumes 46% less silicon area, 24% less energy per inner-product computation and 70% less total interconnect length than its merged arithmetic counterpart in 65 nm CMOS process. In addition, the architecture requires only 4 metal layers out of available 7 layers for signal and power routing. By emulating the on-chip serial-link bus architecture on both designs, it is demonstrated that the proposed design is most suited for high-speed on-chip serial-link bus architecture.

บรรณานุกรม :
Meher, Manas Ranjan , Jong, Ching Chuen , Chang, Chip Hong . (2555). An area and energy efficient inner-product processor for serial-link bus architecture.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Meher, Manas Ranjan , Jong, Ching Chuen , Chang, Chip Hong . 2555. "An area and energy efficient inner-product processor for serial-link bus architecture".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Meher, Manas Ranjan , Jong, Ching Chuen , Chang, Chip Hong . "An area and energy efficient inner-product processor for serial-link bus architecture."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2555. Print.
Meher, Manas Ranjan , Jong, Ching Chuen , Chang, Chip Hong . An area and energy efficient inner-product processor for serial-link bus architecture. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2555.