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A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector
นักวิจัย : Tan, Yung Sern , Yeo, Kiat Seng , Boon, Chirn Chye , Do, Manh Anh
คำค้น : DRNTU::Engineering::Electrical and electronic engineering.
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2554
อ้างอิง : Tan, Y. S., Yeo, K. S., Boon, C. C., & Do, M. A. (2012). A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(6), 1156-1167. , 1549-8328 , http://hdl.handle.net/10220/11325 , http://dx.doi.org/10.1109/TCSI.2011.2173387
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on circuits and systems I : regular papers
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18- μm CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply.

บรรณานุกรม :
Tan, Yung Sern , Yeo, Kiat Seng , Boon, Chirn Chye , Do, Manh Anh . (2554). A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Tan, Yung Sern , Yeo, Kiat Seng , Boon, Chirn Chye , Do, Manh Anh . 2554. "A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Tan, Yung Sern , Yeo, Kiat Seng , Boon, Chirn Chye , Do, Manh Anh . "A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2554. Print.
Tan, Yung Sern , Yeo, Kiat Seng , Boon, Chirn Chye , Do, Manh Anh . A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2554.