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The impact of etch-stop layer for borderless contacts on deep submicron CMOS device performance : a comparative study

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : The impact of etch-stop layer for borderless contacts on deep submicron CMOS device performance : a comparative study
นักวิจัย : Liao, H. , Lee, Pooi See , Goh, L. N. L. , Liu, H. , Sudijono, J. L. , Elgin, Q. , Sanford, C.
คำค้น : DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Thin films.
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2547
อ้างอิง : Liao, H., Lee, P. S., Goh, L. N. L., Liu, H., Sudijono, J. L., Elgin, Q., & Sanford, C. (2004). The impact of etch-stop layer for borderless contacts on deep submicron CMOS device performance—a comparative study. Thin Solid Films, 462-463, 29-33. , 0040-6090 , http://hdl.handle.net/10220/10502 , http://dx.doi.org/10.1016/j.tsf.2004.05.035
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : Thin solid films
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

The impact of etch-stop layers (ESLs) of borderless contact (BLC) on transistor characteristics, especially for NMOSFETs, was studied concerning on the ESL-induced mechanical stress. Two new ESL schemes using dual etch-stop layers: (scheme A) SiON (bottom)/SiN (top) and (scheme B) SiN (bottom)/SiON (top) were studied and implemented into device fabrication. The electrical performance of the N- and PMOSFETs was characterized. It has been found that by using scheme A, a 2.7% improvement of Ion versus Ioff margin as compared with the single-layer process is achieved on NMOSFETs. The scheme A results in a loss of the PMOS margin by 1.4%, which is still within the specifications. However, scheme B, which uses a SiN as the bottom layer, presents a slightly less improvement of process margin (1.7%) on NMOSFETs with much larger loss of process margin (2.3%) on PMOSFETs. Our results suggest that optimization of ESL for borderless contact could play an important role in determining transistor performance for deep submicron CMOS.

บรรณานุกรม :
Liao, H. , Lee, Pooi See , Goh, L. N. L. , Liu, H. , Sudijono, J. L. , Elgin, Q. , Sanford, C. . (2547). The impact of etch-stop layer for borderless contacts on deep submicron CMOS device performance : a comparative study.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Liao, H. , Lee, Pooi See , Goh, L. N. L. , Liu, H. , Sudijono, J. L. , Elgin, Q. , Sanford, C. . 2547. "The impact of etch-stop layer for borderless contacts on deep submicron CMOS device performance : a comparative study".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Liao, H. , Lee, Pooi See , Goh, L. N. L. , Liu, H. , Sudijono, J. L. , Elgin, Q. , Sanford, C. . "The impact of etch-stop layer for borderless contacts on deep submicron CMOS device performance : a comparative study."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2547. Print.
Liao, H. , Lee, Pooi See , Goh, L. N. L. , Liu, H. , Sudijono, J. L. , Elgin, Q. , Sanford, C. . The impact of etch-stop layer for borderless contacts on deep submicron CMOS device performance : a comparative study. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2547.