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Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform

หน่วยงาน Nanyang Technological University, Singapore

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ชื่อเรื่อง : Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform
นักวิจัย : Meher, Pramod Kumar , Mohanty, Basant Kumar , Patra, Jagdish Chandra
คำค้น : DRNTU::Engineering::Computer science and engineering::Hardware::Integrated circuits.
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2551
อ้างอิง : Meher, P. K., Mohanty, B. K., & Patra, J. C. (2008). Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform. IEEE Transactions on Circuits and Systems II: Express Briefs, 55(2), 151-155. , 1549-7747 , http://hdl.handle.net/10220/7104 , http://dx.doi.org/10.1109/TCSII.2007.911801 , 129280
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on circuits and systems II: express briefs
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

A systolic-like modular architecture is presented for hardware-efficient implementation of two-dimensional (2-D) discrete wavelet transform (DWT). The overall computation is decomposed into two distinct stages; where column processing is performed in stage-1, while row processing is performed in stage-2. Using a new data-access scheme and a novel folding technique, the computation of both the stages are performed concurrently for transposition-free implementation of 2-D DWT. The proposed design can offer nearly the same throughput rate, and requires the same or less the number of adders and multipliers as the best of the existing structures. The storage space is found to occupy most of the area in the existing 2-D DWT structures but the proposed structure does not require any on-chip or off-chip storage of input samples or storage/transposition of intermediate output. The proposed one, therefore, involves considerably less hardware complexity compared with the existing structures. Apart from that, it has less duration of cycle period in comparison to the existing structures, and has a latency of cycles while all the existing structures have latency of cycles, the filter order being small compared to the input size.

บรรณานุกรม :
Meher, Pramod Kumar , Mohanty, Basant Kumar , Patra, Jagdish Chandra . (2551). Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Meher, Pramod Kumar , Mohanty, Basant Kumar , Patra, Jagdish Chandra . 2551. "Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Meher, Pramod Kumar , Mohanty, Basant Kumar , Patra, Jagdish Chandra . "Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2551. Print.
Meher, Pramod Kumar , Mohanty, Basant Kumar , Patra, Jagdish Chandra . Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2551.