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Intellectual property authentication by watermarking scan chain in design-for-testability flow

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : Intellectual property authentication by watermarking scan chain in design-for-testability flow
นักวิจัย : Cui, Aijiao , Chang, Chip Hong
คำค้น : DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2551
อ้างอิง : Cui, A., & Chang, C. H. (2008). Intellectual property authentication by watermarking scan chain in design-for-testability flow. Proceedings of 2008 IEEE International Symposium on Circuits and Systems (pp. 2645-2648), Seattle,WA,USA. , http://hdl.handle.net/10220/6320 , http://dx.doi.org/10.1109/ISCAS.2008.4542000
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : -
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

This paper proposes an intellectual property (IP) protection scheme at the Design-for-Testability (DfT) stage of VLSI design flow. Additional constraints generated by the owner’s digital signature have been imposed on the NP-hard problem of ordering the scan cells to achieve a watermarked solution which minimizes the penalty on power and cost of testing. As only the order of the scan cells is varied, the number of test vectors for the desired fault coverage is not affected. The advantage of this scheme is the ownership legitimacy can be publicly authenticated on-site by IP buyers after the chip has been packaged by loading a specific verification code into the scan chain. We propose to integrate the scan chain watermarking with dynamic watermarking of the IP core to make the design hard-to-attack while the ownership is easy-totrace. The proposed scheme is applied to an optimization instance of scan cell ordering targeting at test power reduction. The results on several MCNC benchmarks show that the watermarking scheme has a very low probability of solution coincidence and hence provides strong proof of authorship.

บรรณานุกรม :
Cui, Aijiao , Chang, Chip Hong . (2551). Intellectual property authentication by watermarking scan chain in design-for-testability flow.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Cui, Aijiao , Chang, Chip Hong . 2551. "Intellectual property authentication by watermarking scan chain in design-for-testability flow".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Cui, Aijiao , Chang, Chip Hong . "Intellectual property authentication by watermarking scan chain in design-for-testability flow."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2551. Print.
Cui, Aijiao , Chang, Chip Hong . Intellectual property authentication by watermarking scan chain in design-for-testability flow. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2551.