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Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops
นักวิจัย : Phyu, Myint Wai , Fu, Kang Kang , Goh, Wang Ling , Yeo, Kiat Seng
คำค้น : DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits.
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2552
อ้างอิง : Phyu, M. W., Fu, K. K., Goh, W. L., & Yeo, K. S. (2009). Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1-9. , 1063-8210 , http://hdl.handle.net/10220/6319 , http://dx.doi.org/10.1109/TVLSI.2009.2029116
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on very large scale integration (VLSI) systems
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF.

บรรณานุกรม :
Phyu, Myint Wai , Fu, Kang Kang , Goh, Wang Ling , Yeo, Kiat Seng . (2552). Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Phyu, Myint Wai , Fu, Kang Kang , Goh, Wang Ling , Yeo, Kiat Seng . 2552. "Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Phyu, Myint Wai , Fu, Kang Kang , Goh, Wang Ling , Yeo, Kiat Seng . "Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2552. Print.
Phyu, Myint Wai , Fu, Kang Kang , Goh, Wang Ling , Yeo, Kiat Seng . Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2552.