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Area-saving technique for low-error redundant binary fixed-width multiplier implementation

หน่วยงาน Nanyang Technological University, Singapore

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ชื่อเรื่อง : Area-saving technique for low-error redundant binary fixed-width multiplier implementation
นักวิจัย : Juang, Tso Bing , Wei, Chi Chung , Chang, Chip Hong
คำค้น : DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2552
อ้างอิง : Juang, T. B., Wei, C. C., & Chang, C. H. (2009). Area-saving technique for low-error redundant binary fixed-width multiplier implementation. International Symposium on Integrated Circuits (12th:2009:Singapore) , http://hdl.handle.net/10220/6356 , http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403938
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : -
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

A recently proposed architecture of redundant binary fixed-width multiplier was shown to outperform several normal binary fixed-width multipliers in terms of accuracy. However, its merit due to the carry-free addition property of the binary signed digit (BSD) partial products has been offset by the high area overhead of the redundant binary full adder tree. To achieve low–error fixed-width multiplication with smaller silicon area, we propose a hybrid structure which makes use of dual polarity high order column compressors and (3:2) counters to parallelly reduce the positive and negative BSD partial products. Our proposed technique has led to a fixed-width multiplier architecture with the same accuracy and up to 42% area saving for 10×10-bit multiplication over the conventional redundant binary fixed-width multiplier architecture in 0.18 m CMOS standard cell implementation under the same timing constraint.

บรรณานุกรม :
Juang, Tso Bing , Wei, Chi Chung , Chang, Chip Hong . (2552). Area-saving technique for low-error redundant binary fixed-width multiplier implementation.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Juang, Tso Bing , Wei, Chi Chung , Chang, Chip Hong . 2552. "Area-saving technique for low-error redundant binary fixed-width multiplier implementation".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Juang, Tso Bing , Wei, Chi Chung , Chang, Chip Hong . "Area-saving technique for low-error redundant binary fixed-width multiplier implementation."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2552. Print.
Juang, Tso Bing , Wei, Chi Chung , Chang, Chip Hong . Area-saving technique for low-error redundant binary fixed-width multiplier implementation. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2552.