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A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two’s complement converter

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two’s complement converter
นักวิจัย : He, Yajuan , Chang, Chip Hong
คำค้น : DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2551
อ้างอิง : He, Y., & Chang, C. H. (2008). A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two’s complement converter. IEEE Transactions on Circuits and Systems Part 1 Regular Papers. 55(1), 336-346. , 1549-8328 , http://hdl.handle.net/10220/6328 , http://dx.doi.org/10.1109/TCSI.2007.913610
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on circuits and systems part 1 regular papers
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

This paper presents an efficient reverse converter for transforming the redundant binary (RB) representation into two’s complement form. The hierarchical expansion of the carry equation for the reverse conversion algorithm creates a regular multilevel structure, from which a high-speed hybrid carry-lookahead/ carry-select (CLA/CSL) architecture is proposed to fully exploit the redundancy of RB encoding for VLSI efficient implementation. The optimally designed CSL sections interleaved evenly in the mixed-radix CLA network to boost the performance of the reverse converter well above those designed based on a homogeneous type of carry propagation adder. The logical effort characterization captures the effect of circuit’s fan-in, fan-out and transistor sizing on performance, and the evaluation shows that our proposed architecture leads to the fastest design. A 64-bit transistor-level circuit implementation of our proposed reverse converter and that of its most competitive contender were simulated to validate the logical effort delay model. The pre- and post-layout HSPICE simulation results reveal that our new converter expends at least two times less energy (power–delay product) than the competitor circuit and is capable of completing a 64-bit conversion in 829 ps and dissipates merely 5.84 mW at a data rate of 1 GHz and a supply voltage of 1.8 V in TSMC 0.18- m CMOS technology.

บรรณานุกรม :
He, Yajuan , Chang, Chip Hong . (2551). A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two’s complement converter.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
He, Yajuan , Chang, Chip Hong . 2551. "A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two’s complement converter".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
He, Yajuan , Chang, Chip Hong . "A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two’s complement converter."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2551. Print.
He, Yajuan , Chang, Chip Hong . A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two’s complement converter. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2551.