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IP watermarking using incremental technology mapping at logic synthesis level

หน่วยงาน Nanyang Technological University, Singapore

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ชื่อเรื่อง : IP watermarking using incremental technology mapping at logic synthesis level
นักวิจัย : Cui, Aijiao , Chang, Chip Hong , Tahar, Sofiène
คำค้น : DRNTU::Engineering::Electrical and electronic engineering
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2551
อ้างอิง : Cui, A., Chang, C. H., & Tahar, S. (2008). IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27(9), 1565-1570. , 0278-0070 , http://hdl.handle.net/10220/6259 , http://dx.doi.org/10.1109/TCAD.2008.927732
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on computer-aided design of integrated circuits and systems
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. The headroom of each disjoint closed cone is evaluated based on its slack and slack sustainability. The notion of slack sustainability in conjunction with an embedding threshold enables closed cones in the critical path to be qualified as watermark hosts if their slacks can be better preserved upon remapping. The watermark is embedded by remapping only qualified disjoint closed cones randomly selected and templates constrained by the signature. This parametric formulation provides a means to capitalize on the headroom of a design to increase the signature length or strengthen the watermark resilience. With the master design, the watermarked design can be authenticated as in nonoblivious media watermarking. Experimental results show that the design can be efficiently marked by our method with low overhead.

บรรณานุกรม :
Cui, Aijiao , Chang, Chip Hong , Tahar, Sofiène . (2551). IP watermarking using incremental technology mapping at logic synthesis level.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Cui, Aijiao , Chang, Chip Hong , Tahar, Sofiène . 2551. "IP watermarking using incremental technology mapping at logic synthesis level".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Cui, Aijiao , Chang, Chip Hong , Tahar, Sofiène . "IP watermarking using incremental technology mapping at logic synthesis level."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2551. Print.
Cui, Aijiao , Chang, Chip Hong , Tahar, Sofiène . IP watermarking using incremental technology mapping at logic synthesis level. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2551.