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High-level synthesis algorithm for the design of reconfigurable constant multiplier

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : High-level synthesis algorithm for the design of reconfigurable constant multiplier
นักวิจัย : Chen, Jiajia , Chang, Chip Hong
คำค้น : DRNTU::Engineering::Electrical and electronic engineering
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2552
อ้างอิง : Chen, J., & Chang, C. H. (2009). High-level synthesis algorithm for the design of reconfigurable constant multiplier. IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, 28(12), 1844-1856. , 0278-0070 , http://hdl.handle.net/10220/6230 , http://dx.doi.org/10.1109/TCAD.2009.2030446
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on computer-aided design of integrated circuits and systems
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

Multiplying a signal by a known constant is an essential operation in digital signal processing algorithms. In many application scenarios, an input or output signal is repeatedly multiplied by several predefined constants at different instances. These temporal redundancies can be exploited for the design of an efficient reconfigurable constant multiplier (RCM). An RCM achieves greater hardware savings than the conventional multiple constant multiplication architecture, limited only by the available latency of the subsystem. Motivated by a number of lucrative examples, this paper presents a new high-level design methodology for RCM. Common subexpressions in the preset constants represented in minimum signed-digit system are first eliminated to obtain a minimum depth multiroot directed acyclic graph (DAG). The DAG is converted into a primitive data flow graph (DFG) where mobile adders are identified. By scheduling each mobile adder into a control step within its legitimate time window with the minimum opportunity cost, mutually exclusive adders can be merged with significantly reduced adder and multiplexing cost. The opportunity cost for each scheduling decision is assessed by the probability displacement and disparity measures of the scheduled node as well as its predecessors and successors in the DFG. The algorithm is runtime efficient as exhaustive search for the best fusion of independently optimized constant multipliers has been avoided. Simulation results on randomly generated 12-b constant sets show that the solutions generated by the proposed algorithm are on average 19% to 25% more area–time efficient than the best reported solutions.

บรรณานุกรม :
Chen, Jiajia , Chang, Chip Hong . (2552). High-level synthesis algorithm for the design of reconfigurable constant multiplier.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Chen, Jiajia , Chang, Chip Hong . 2552. "High-level synthesis algorithm for the design of reconfigurable constant multiplier".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Chen, Jiajia , Chang, Chip Hong . "High-level synthesis algorithm for the design of reconfigurable constant multiplier."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2552. Print.
Chen, Jiajia , Chang, Chip Hong . High-level synthesis algorithm for the design of reconfigurable constant multiplier. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2552.