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Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler
นักวิจัย : Yeo, Kiat Seng , Boon, Chirn Chye , Lim, Wei Meng , Do, Manh Anh , Krishna, Manthena Vamshi
คำค้น : DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits.
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2553
อ้างอิง : Yeo, K. S, Boon, C. C., Lim, W. M., Do, M. A. & Krishna, M. V. (2010). Design and Analysis of Ultra low power True single phase clock CMOS 2/3 prescaler. IEEE Transactions on Circuits and Systems I: Regular Paper, 57(1), 72-82. , 1549-8328 , http://hdl.handle.net/10220/6213 , http://dx.doi.org/10.1109/TCSI.2009.2016183
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on circuits and systems—I
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a Chartered 0.18 m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.

บรรณานุกรม :
Yeo, Kiat Seng , Boon, Chirn Chye , Lim, Wei Meng , Do, Manh Anh , Krishna, Manthena Vamshi . (2553). Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Yeo, Kiat Seng , Boon, Chirn Chye , Lim, Wei Meng , Do, Manh Anh , Krishna, Manthena Vamshi . 2553. "Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Yeo, Kiat Seng , Boon, Chirn Chye , Lim, Wei Meng , Do, Manh Anh , Krishna, Manthena Vamshi . "Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2553. Print.
Yeo, Kiat Seng , Boon, Chirn Chye , Lim, Wei Meng , Do, Manh Anh , Krishna, Manthena Vamshi . Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2553.