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Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

หน่วยงาน Nanyang Technological University, Singapore

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ชื่อเรื่อง : Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications
นักวิจัย : Sia, Choon Beng , Ong, Beng Hwee , Chan, Kwok Wai , Yeo, Kiat Seng , Ma, Jianguo , Do, Manh Anh
คำค้น : DRNTU::Engineering::Electrical and electronic engineering.
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2548
อ้างอิง : Sia, C. B., Ong, B. H., Chan, K. W., Yeo, K. S., Ma, J. G., & Do, M. A. (2005). Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications. IEEE Transactions on Electron Devices, 52(12), 2559-2567. , 0018-9383 , http://hdl.handle.net/10220/4663 , http://dx.doi.org/10.1109/TED.2005.859638
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on electron devices
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-µm RFCMOS technology, experimental results in this paper reveal that inductors’ core diameters must be adequately large, more than 100 µm, to ensure high quality factor characteristics and their conductor spacing should be minimal to obtain larger per unit area inductance value. A novel design methodology which optimizes the conductor width of inductors allows alignment of their peak quality factor to the circuit’s operating frequency, enhancing the gain, input/output matching characteristics and noise figure of a giga-hertz amplifier.

บรรณานุกรม :
Sia, Choon Beng , Ong, Beng Hwee , Chan, Kwok Wai , Yeo, Kiat Seng , Ma, Jianguo , Do, Manh Anh . (2548). Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Sia, Choon Beng , Ong, Beng Hwee , Chan, Kwok Wai , Yeo, Kiat Seng , Ma, Jianguo , Do, Manh Anh . 2548. "Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Sia, Choon Beng , Ong, Beng Hwee , Chan, Kwok Wai , Yeo, Kiat Seng , Ma, Jianguo , Do, Manh Anh . "Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2548. Print.
Sia, Choon Beng , Ong, Beng Hwee , Chan, Kwok Wai , Yeo, Kiat Seng , Ma, Jianguo , Do, Manh Anh . Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2548.