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Scalable model of on-wafer interconnects for high-speed CMOS ICs

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : Scalable model of on-wafer interconnects for high-speed CMOS ICs
นักวิจัย : Shi, Xiaomeng , Yeo, Kiat Seng , Ma, Jianguo , Do, Manh Anh , Li, Erping
คำค้น : DRNTU::Engineering::Electrical and electronic engineering.
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2549
อ้างอิง : Shi, X., Yeo, K. S., Ma, J. G., Do, M. A., & Li, E. (2006). Scalable model of on-wafer interconnects for high-speed CMOS ICs. IEEE Transactions on Advanced Packaging, 29(4), 770-776. , 1521-3323 , http://hdl.handle.net/10220/4713 , http://dx.doi.org/10.1109/TADVP.2006.884781
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on advanced packaging
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two- blocks together, the lumped model can characterize the distributed effects. Besides, the elaborately proposed model characterizes the frequency-variant characteristics with frequency-independent components. Thus, the model can be easily plugged into commercial computer-aided design tools. By adopting a newly invented optimization algorithm, namely, particle swarm optimization (PSO), the model parameters are extracted and formulated as empirical expressions. Therein, with each set of the geometrical parameters, the interconnect behaviors can be accurately predicted. The accuracy of the model is validated by comparisons with the on-wafer measurements up to 30 GHz. Moreover, the scalability of the proposed model is also discussed.

บรรณานุกรม :
Shi, Xiaomeng , Yeo, Kiat Seng , Ma, Jianguo , Do, Manh Anh , Li, Erping . (2549). Scalable model of on-wafer interconnects for high-speed CMOS ICs.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Shi, Xiaomeng , Yeo, Kiat Seng , Ma, Jianguo , Do, Manh Anh , Li, Erping . 2549. "Scalable model of on-wafer interconnects for high-speed CMOS ICs".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Shi, Xiaomeng , Yeo, Kiat Seng , Ma, Jianguo , Do, Manh Anh , Li, Erping . "Scalable model of on-wafer interconnects for high-speed CMOS ICs."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2549. Print.
Shi, Xiaomeng , Yeo, Kiat Seng , Ma, Jianguo , Do, Manh Anh , Li, Erping . Scalable model of on-wafer interconnects for high-speed CMOS ICs. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2549.