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A review of 0.18-µm full adder performances for tree structured arithmetic circuits

หน่วยงาน Nanyang Technological University, Singapore

รายละเอียด

ชื่อเรื่อง : A review of 0.18-µm full adder performances for tree structured arithmetic circuits
นักวิจัย : Chang, Chip Hong , Gu, Jiang Min , Zhang, Mingyan
คำค้น : DRNTU::Engineering::Electrical and electronic engineering
หน่วยงาน : Nanyang Technological University, Singapore
ผู้ร่วมงาน : -
ปีพิมพ์ : 2548
อ้างอิง : Chang, C. H., Gu, J. M., & Zhang, M. (2005). A review of 0.18-µm full adder performances for tree structured arithmetic circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(6), 686-695. , 1063-8210 , http://hdl.handle.net/10220/6013 , http://dx.doi.org/10.1109/TVLSI.2005.848806
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : IEEE transactions on very large scale integration (VLSI) systems
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation circuits of the proposed full adder are designed with hybrid logic styles. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem. As full adders are frequently employed in a tree structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is introduced to evaluate the full adders in a realistic application environment. A systematic and elegant procedure to scale the transistor for minimal power-delay product is proposed. The circuits being studied are optimized for energy efficiency at 0.18-µm CMOS process technology. With the proposed simulation environment, it is shown that some survival cells in stand alone operation at low voltage may fail when cascaded in a larger circuit, either due to the lack of drivability or unsatisfactory speed of operation. The proposed hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The increase in the transistor count of its complementary CMOS output stage is compensated by its area efficient layout. Therefore, it remains one of the best contenders for designing large tree structured arithmetic circuits with reduced energy consumption while keeping the increase in area to a minimum.

บรรณานุกรม :
Chang, Chip Hong , Gu, Jiang Min , Zhang, Mingyan . (2548). A review of 0.18-µm full adder performances for tree structured arithmetic circuits.
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Chang, Chip Hong , Gu, Jiang Min , Zhang, Mingyan . 2548. "A review of 0.18-µm full adder performances for tree structured arithmetic circuits".
    กรุงเทพมหานคร : Nanyang Technological University, Singapore.
Chang, Chip Hong , Gu, Jiang Min , Zhang, Mingyan . "A review of 0.18-µm full adder performances for tree structured arithmetic circuits."
    กรุงเทพมหานคร : Nanyang Technological University, Singapore, 2548. Print.
Chang, Chip Hong , Gu, Jiang Min , Zhang, Mingyan . A review of 0.18-µm full adder performances for tree structured arithmetic circuits. กรุงเทพมหานคร : Nanyang Technological University, Singapore; 2548.