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Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging

หน่วยงาน Universiti Sains Malaysia, Malaysia

รายละเอียด

ชื่อเรื่อง : Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging
นักวิจัย : Tan , Ai Heong
คำค้น : TK1-9971 Electrical engineering. Electronics. Nuclear engineering
หน่วยงาน : Universiti Sains Malaysia, Malaysia
ผู้ร่วมงาน : -
ปีพิมพ์ : 2558
อ้างอิง : http://eprints.usm.my/40931/1/TAN_AI_HEONG_24_pages.pdf , Tan , Ai Heong (2015) Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging. Masters thesis, Universiti Sains Malaysia.
ที่มา : -
ความเชี่ยวชาญ : -
ความสัมพันธ์ : http://eprints.usm.my/40931/
ขอบเขตของเนื้อหา : -
บทคัดย่อ/คำอธิบาย :

In this miniaturization era, previously, shrinking the technology node was used in order to maintain and improve the electrical performance of a device. However, this method is getting difficult due to the limitation of Silicon (Si) atomic size of the material in designing the integrated circuit (IC). Moreover, the signaling techniques play a crucial role in determining the overall performance of a device. Thus, this thesis explores an innovative concept of vertical side-chip interconnection (VSCI) for 3 dimension (3D) packaging to improve the performance of IC. The electrical performance of the proposed vertical side-chip stacked package is discussed in order to optimize the structure of VSCI. Optimization of VSCI structure is based on stacked die package application with the trending of through silicon via (TSV) signal orientation, TSV signal to ground ratio and TSV signal pitch impact to the overall signal integrity performance. Then, this thesis had underscored the electrical performance of the aforementioned stacked die packages from signal integrity perspective in terms of impedance matching, noise shielding and electrical losses. Then, the sensitivity study of channel termination on vertical side-chip interconnection (VSCI) was carried out. The conventional 3D integrated system with solder bump and surface activated bonding (SAB) technology also was investigated as comparison with VSCI. The trends of eye height opening and one of the critical signaling parameters were analyzed based on transmission channel length, input rise time, receiver device capacitance and termination resistance factors. Finally, full wave simulation using 3D electromagnetic field solvers and transient analysis results showed the feasibility of VSCI as alternative method to achieve comparable electrical performance with the conventional solder bump and SAB interconnection models at 100Gbps transfer rate. The simulation results showed potential solution space of VSCI for weak receiver termination to achieve more 350mV eye height opening (based on 1V supply voltage) at 30Gbps.

บรรณานุกรม :
Tan , Ai Heong . (2558). Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging.
    กรุงเทพมหานคร : Universiti Sains Malaysia, Malaysia.
Tan , Ai Heong . 2558. "Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging".
    กรุงเทพมหานคร : Universiti Sains Malaysia, Malaysia.
Tan , Ai Heong . "Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging."
    กรุงเทพมหานคร : Universiti Sains Malaysia, Malaysia, 2558. Print.
Tan , Ai Heong . Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging. กรุงเทพมหานคร : Universiti Sains Malaysia, Malaysia; 2558.