ridm@nrct.go.th   ระบบคลังข้อมูลงานวิจัยไทย   รายการโปรดที่คุณเลือกไว้

Goh, Wang Ling
หน่วยงาน Nanyang Technological University, Singapore
จำนวนงานวิจัยจำแนกรายปี
บุคคลที่เคยร่วมงานวิจัย
ความเชี่ยวชาญ
ปี
# พ.ศ. จำนวน
1 2555 14
2 2554 2
3 2552 6
4 2551 3
5 2542 1
6 2540 1
ผลงานวิจัย
# หัวเรื่อง
ปี พ.ศ. 2555
1 130-GHz on-chip meander slot antennas with stacked dielectric resonators in standard CMOS technology
2 A 60-V, > 225°C half-bridge driver for piezoelectric acoustic transducer, on SOI CMOS
3 Comparing analytical, micromagnetic and statistical channel models at 4 Tcbpsi patterned media recording
4 Distributed modeling of six-port transformer for millimeter-wave SiGe BiCMOS circuits design
5 A hardware-efficient all-digital transmitter architecture for acoustic borehole telemetry systems
6 A PAE of 17.5% Ka-band balanced frequency doubler with conversion gain of 20 dB
7 A 9% power efficiency 121-to-137GHz phase-controlled push-push frequency quadrupler in 0.13μm SiGe BiCMOS
8 800 nW 43 nV/[radical]Hz neural recording amplifier with enhanced noise efficiency factor
9 A 5-Gb/s automatic gain control amplifier with temperature compensation
10 A 27–41 GHz frequency doubler with conversion gain of 12 dB and PAE of 16.9%
11 A D-band cascode amplifier with 24.3 dB gain and 7.7 dBm output power in 0.13 μm SiGe BiCMOS technology
12 A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels
13 Two-write WOM-codes for non-volatile memories
14 A 10-Gb/s inductor-less variable gain amplifier with a linear-in-dB characteristic and DC-offset cancellation
ปี พ.ศ. 2554
15 A dual-feedforward carrier-modulated second-order class-D amplifier with improved THD
16 Time-domain analysis of intermodulation distortion of closed-loop class-D amplifiers
ปี พ.ศ. 2552
17 Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
18 A low-noise multi-GHz CMOS multiloop ring oscillator with coarse and fine frequency tuning
19 An enhanced low-power high-speed adder for error-tolerant application
20 A general decoding framework for high-rate LDPC codes
21 Ultra low-power full-adder for biomedical applications
22 Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops
ปี พ.ศ. 2551
23 Dual nanowire silicon MOSFET with silicon bridge and TaN gate
24 Body-bootstrapped-buffer circuit for CMOS static power reduction
25 A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes
ปี พ.ศ. 2542
26 The manufacture and performance of diodes made in dielectrically isolated silicon substrates containing buried metallic layers
ปี พ.ศ. 2540
27 Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers